This article evaluates the proficiency of 11 contemporary Large Language Models (LLMs) in performing electronic circuit analysis. Utilizing OpenCode, an open-source agentic framework, the LLMs are tasked with analyzing a clock generator’s resistor-capacitor (RC) network defined in a KiCad 9.0… Continue Reading
Some days ago I ordered a testing PCB from PCBWAY, and today the package has arrived! FRONT: BACK: As discussed in the previous article, this is a test-board for the future PCIe card with Agilex 3 FPGA. But presently –… Continue Reading
In hardware design, tedious manual data entry is a common bottleneck. I recently explored how the ‘AI revolution’ – specifically LLMs and GitHub Copilot – could automate a specific, repetitive task: importing BGA pad-to-die lengths into KiCad 9. The input… Continue Reading
AGILA will be a new open-source board with the Altera Agilex 3 FPGA, 2 GB to 8 GBof LPDDR4 RAM and the PCI-Express interface. The Agilex 3 FPGA includes hard-IP support for PCI- Express interface up to Gen3 x4 and… Continue Reading
The picture below is an extract from Power-Supply Block Diagram of the official Agilex 3 Devkit. The FPGA requires multiple power supply levels: from 0.75V to 3.3V. Specification is found in altera document Power Management User Guide: Agilex™ 3 FPGAs… Continue Reading
Theoretically, Agilex 3 FPGA does not require any external clock signals to load bitstream and to operate an (asynchronous) user design. However, in practice, all designs will need to supply some clock signals for use in EMIF (e.g. LPDDR4) or… Continue Reading
What the local company manager expects:1. Make all developers use gen-AI tools for coding2. Expect productivity increase 3. Profit!! What the AI-tooling company plans: 1. Make all developers use gen-AI tools for coding2. When most are dependent, decrease the quality… Continue Reading
Agilex 3 FPGA supports loading of the configuration bitstream by multiple methods. A method is selected by 3 strapping pins MSEL[2:0] (these are multi-purpose strapping pins). The common methods are: The recommended vendor of QSPI flash is Micron because of… Continue Reading
Agilex 3 FPGA supports PCI-Express via its four GTS transceiver links. Each GTS physical link (tx+rx) supports up to 12.5Gbps transfer speed. On top of the GTS transceivers the FPGA implements hardened IPs for PCI-Express 3.0 x1-x2-x4, Ethernet 10 Gbe… Continue Reading
Presently (2025) there are two perspective busses for connecting DRAM devices in embedded systems: The DDR3L supports traditional DDR multidrop bus topology with VTT termination and multiple memory devices sharing the address/control bus. The LPDDR4 is a completely different protocol… Continue Reading